In the field of semiconductor devices used for power application, a vertical type MOSFET having a super junction (SJ) structure which can be designed to have a high withstanding voltage and a low ON-resistance is disclosed in JP-A-2002-184985 (Patent Document 1) and JP-A-2000-260984 (Patent Document 2), for example.
FIG. 12 is a perspective view schematically showing a vertical type MOSFET 90 having an SJ structure disclosed in the Patent Document 1. In the vertical type MOSFET 90 formed in a semiconductor substrate 1, a pn column formed portion comprising a repetitive pattern of a p-conduction type region 21 and an n-conduction type region 22 on an n+-conduction type layer 11 serving as a drain corresponds to an SJ structure. Particularly, FIG. 12 shows one end portion of the vertical type MOSFET 90, and a repetitive pattern of a stripe-shaped p-conduction type region 21 and a stripe-shaped n-type conduction region 22 and a repetitive pattern of a stripe-shaped source S and a stripe-shaped gate G are arranged in the rightward direction of FIG. 12. Furthermore, the left side of FIG. 12 shows the end portion of the vertical type MOSFET 90, and an n-conduction type region 23 having a larger width than the n-conduction type regions 22 of the pn column is formed so as to extend to the surface of the semiconductor substrate 1.
In FIG. 12, reference numeral 31 represents a p-conduction type layer serving as a body layer, reference numeral 32 represents a p-conduction type region serving as a channel, and reference numeral 33 represents an n-conduction type region serving as a source. Furthermore, reference numeral 41 represents a gate oxide film formed in a trench, and reference numeral 42 represents a trench gate electrode. Each striped trench gate electrode 42 is disposed in parallel to the striped pn column so as to project into the n-conduction type region 22 of the pn column. Reference numeral 10 represents an alignment key for the positioning between the trench gate electrode 42 and the n-conduction type region 22.
In the vertical MOSFEfT 90 having the SJ structure of FIG. 12, electrons flowing out from the n-conduction type region 33 serving as the source pass through the channel formed in the p-conduction type region 32 and the p-conduction type layer 31 around the trench gate electrode 42 and flow into the n-conduction type region 22 of the pn column which serves as a drift region. Accordingly, the concentration of impurities in the n-conduction type region 22 serving as the drift region can be increased, and the ON-resistance of the vertical type MOSFET 90 of FIG. 12 can be lowered. On the other hand, under an OFF-state, the pn column is completely depleted so that the withstanding voltage can be increased. As described above, a vertical type MOSFET having desired ON-resistance and withstanding voltage can be achieved by properly setting the width, depth and impurity-concentration of the pn column.
FIG. 13 shows another example of the vertical type MOSFET having the SJ structure and is a perspective view schematically showing the vertical MOSFET 91 disclosed in the Patent Document 2. In the vertical type MOSFET 91 shown in FIG. 13, the similar parts to the respective constituent elements of the vertical type MOSFET 90 of FIG. 12 are represented by the same reference numerals.
The vertical type MOSFET 91 of FIG. 13 is different from the vertical type MOSFET 90 of FIG. 12 in that an n−-conduction type layer 37 is added to the pn column. Furthermore, in the vertical type MOSFET 91 of FIG. 13, the repetitive pattern of the striped p-conduction type regions 21 and the striped n-conduction type regions 22 constituting the pn column and each trench gate electrode 42 are disposed to cross each other. The tip of each trench gate electrode 42 is located within the n−-conduction type layer 37, and does not project into the pn column.
In the vertical type MOSFET 91 having the SJ structure of FIG. 13, electrons flowing out from the n-conduction type regions 33 serving as the sources pass through channels formed in the p-conduction type regions 32 around the trench gate electrodes 42, and then flow into the n−-conduction type layer 37 serving as the drift region. and the n-conduction type region 22 of the pn column.
FIGS. 14A to 14D and FIGS. 15A to 15C are cross-sectional views showing a method of manufacturing the vertical type MOSFET 90 shown in FIG. 12. The cross-sectional views of FIGS. 14A to 15C show the flow of the manufacturing process of the vertical type MOSFET 90 when viewed from the front side in the perspective view of FIG. 12.
In the manufacturing process of the vertical type MOSFET 90, a semiconductor substrate (wafer) 1 in which an n-conduction type layer 20 is formed on an n+-conduction type layer 11 is prepared, and then trenches 20t are first formed in the semiconductor substrate 1 as shown in FIG. 14A, whereby the n-conduction type layer 20 is divided into n-conduction type regions 22 constituting a pn column and a wide n-conduction type region 23 at the end portion. In this trench forming step, an alignment key 10 comprising shallow trenches is also formed in advance.
Subsequently, p-conduction type layers are formed to be embedded in the trenches 20t as shown in FIG. 14B by an epitaxial method, and then the surface of the semiconductor substrate thus formed is flattened. Accordingly, the p-conduction type layers embedded in the trenches 20t serve as p-conduction type regions 21, whereby the pn column is completed. The pn column thus formed serves as an SJ (Super Junction) structure. During the formation of the p-conduction type layers, the alignment key 10 is masked.
Subsequently, a p-conduction type layer 31 serving as a body layer is further formed on the semiconductor substrate 1 by the epitaxial method as shown in FIG. 14C.
Subsequently, as shown in FIG. 14D, ion-implantation of n-type impurities is applied to the p-conduction type layer 31 on the wide n-conduction type region 23 at the end portion so that the wide n-conduction type region 23 at the end portion reaches the upper surface of the semiconductor substrate 1.
Subsequently, as shown in FIG. 15A, a predetermined area of the p-conduction type layer 31 is masked, and ion implantation of impurities is selectively carried out to form p-conduction type regions 32 serving as channels and n-conduction type regions 33 serving as sources.
Subsequently, as shown in FIG. 15B, alignment (positioning) is carried out by using the alignment key 10 so that the stripes of the trenches to be formed are located within the n-conduction type regions 22 of the pn column, whereby the trenches projecting into the pn column at the tips thereof are formed. Thereafter, the trench side walls are oxidized to form gate oxide film 41, and gate electrodes 42 are filled in the trenches.
Finally, as shown in FIG. 15C, a source electrode 6 is formed through interlayer insulating film 5, and a drain electrode 7 is formed on the opposite side to the source electrode 6, thereby completing the formation of the vertical type MOSFET 90 shown in FIG. 12.
In the manufacturing process of the semiconductor device, a plurality of semiconductor devices having the same structure are normally formed on one semiconductor substrate (wafer), and then cut out into individual chips, whereby the plural semiconductor devices are formed from one semiconductor substrate (wafer). In the above manufacturing process, many vertical MOSFETs 90 having the same structure shown in FIG. 12 are likewise formed in one semiconductor substrate (wafer) 1, and finally cut out into individual chips, thereby manufacturing plural vertical MOSFETs 90 of FIG. 12
In the manufacturing process shown in FIGS. 14A to FIG. 15C, the trench gate electrodes 42 are formed to be in alignment with the n-conduction type regions 22 of the pn column. Accordingly, the step of forming the alignment key 10 and the step of masking the alignment key 10 are needed as shown in FIGS. 14A and 14B. In the trench forming step for the gate electrodes of FIG. 15B, the mask for forming the trenches for the gate electrodes is needed to be aligned with the alignment key 10. Therefore, the manufacturing cost is increased by the steps relevant to the alignment.
On the other hand, the vertical type MOSFET 91 of FIG. 13 does not need the alignment of the trench gate electrodes 42 with the pn column because the n−-conduction type layer 37 is additionally formed on the pn column. However, in this case, it is needed to form the n−-conduction layer 37, so that the manufacturing cost is also increased.